1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly to a dynamic random access memory (DRAM) eliminating the need for refresh.
2. Description of the Background Art
A configuration of a conventional DRAM memory cell is explained with reference to FIG. 11.
In FIG. 11, a silicon substrate 101 is provided with an element isolating region 102 for separating element regions from each other. An n type well 103 and a p type well 104 are provided in silicon substrate 101 beneath the element regions. A gate oxide film 105 is placed in contact with the silicon substrate where an element is to be formed. A doped polysilicon 106 is located on gate oxide film 105, and a WSi layer 107 and a two-layer film 108 formed of silicon oxide film and silicon nitride film are arranged thereon. A gate electrode 109 includes the above-described doped polysilicon 106, WSi layer 107 and two-layer film 108. Gate electrode 109 has its sidewall insulated by a sidewall 110.
An n+ type source/drain region 111 is disposed in p type well 104, and a p+ type source/drain region 112 is disposed in n type well 103. An interlayer silicon oxide film 113 is arranged to cover the above-described structure, and a buried contact 114 on silicon substrate is placed to penetrate interlayer silicon oxide film 113 in a vertical direction. Similarly, a poly-pad 115 on silicon substrate is arranged. An interlayer silicon oxide film 118 is disposed to cover upper ends of buried contact 114 on silicon substrate and poly-pad 115 on silicon substrate. A tungsten bit line contact 120 and a bit line 119 are arranged to penetrate interlayer silicon oxide film 118 in a vertical direction, to electrically connect with the source/drain region thereunder. An interlayer silicon oxide film 126 is placed to cover them. Penetrating interlayer silicon oxide films 126 and 118 in a vertical direction, a buried contact 127 and a poly-pad 128 are arranged to electrically connect with underlying buried contact 114 on silicon substrate and poly-pad 115 on silicon substrate, respectively.
An interlayer silicon nitride film/interlayer silicon oxide film 129 is further arranged to cover the above-described structure. A storage node 130 is located in interlayer silicon nitride film/interlayer silicon oxide film 129, and a dielectric film 131 is arranged thereon, thereby forming a cylindrical capacitor 132. An interlayer silicon oxide film 133 is arranged to cover the cylindrical capacitor and others. A metal contact 134 is placed to penetrate interlayer silicon oxide film 133 to electrically connect to an electrode of the cylindrical capacitor 132. A metal interconnection 135 is located on interlayer silicon oxide film 133, continuously on metal contact 134. An interlayer silicon oxide film 136 is arranged to cover metal interconnection 135, and a metal contact 137 is placed to penetrate the relevant film 136. A metal interconnection 138 is placed thereon, and a passivation film 139 is further placed to cover metal interconnection 138.
With the structure as described above, an access transistor including gate electrode 109 is turned on/off as it receives a signal from a word line (not shown) at the gate electrode, and controls transfer of charges between bit line 119 and capacitor 132. In a state where charges are accumulated on the capacitor, the storage node has its potential maintained at a prescribed high potential, and a stored state of digital information is maintained. That is, when capacitor 132 is charged, the storage node is in a high potential state, which is assumed to be, e.g., an on state. By comparison, when capacitor 132 is uncharged, the storage node is in a zero potential state, which is assumed to be, e.g., an off state. A DRAM thus serves as a storage device which stores binary information by accumulating charges on a capacitor.
With the above-described structure, however, the charges accumulated on the capacitor would leak from the storage node via the well to the semiconductor substrate over a prescribed period of time, resulting in loss of charges of the capacitor. Such leakage and loss of charges correspond to loss of stored information. To prevent this, in a DRAM, refresh has been repeated at prescribed periods to restore the charges lost from the capacitor, before complete loss of the charges. As such, the DRAM requires a circuit for the refresh. A large amount of power is consumed for the refresh, causing an increase of the power consumption of the DRAM.
A static random access memory (SRAM) is known to make such refresh unnecessary. With the SRAM, however, six transistors per memory cell have to be formed on a silicon substrate. This considerably increases the memory cell size compared to the case of the DRAM.